I was not expecting the CT scan to be able to identify the cores within the die.
But now I think about it, the metal layers (especially traces carrying power) are probably think enough, and different enough to show up. And even just power distribution is enough for the shape of the cores to be visible.
You can typically see the L1/L2 SRAM cache regions just by looking for continuous patterns, then try to divide it into the number of cores or core groups you're looking for.
This is only applicable to die photographs of the silicon layer.
For CT scans, which use X-rays, the visible structure is very likely due to the metallic (copper) interconnect, clock- and power-delivery layers, which are generally quite different from the underlying transistors.
These layers are larger-scale, and copper also absorbs X-rays much more strongly than silicon.
How neat! Would be cool to see the side by sides of equivalent tier CPU’s throughout the generations
LTT Labs are writing up a lot of nice content of late.
Sadly posts from one of their employees, Lucas, are auto-dead and don't get seen which is sad given their effort and quality.
I wonder why? Genuinely, not sarcastically
The author of the linked article is Lucas...
I was not expecting the CT scan to be able to identify the cores within the die.
But now I think about it, the metal layers (especially traces carrying power) are probably think enough, and different enough to show up. And even just power distribution is enough for the shape of the cores to be visible.
You don't even need a CT to identify the cores; they are already quite obvious in regular die photos as repeated areas.
https://commons.wikimedia.org/wiki/File:Intel_Core_i9-13900K...
You can typically see the L1/L2 SRAM cache regions just by looking for continuous patterns, then try to divide it into the number of cores or core groups you're looking for.
This is only applicable to die photographs of the silicon layer.
For CT scans, which use X-rays, the visible structure is very likely due to the metallic (copper) interconnect, clock- and power-delivery layers, which are generally quite different from the underlying transistors.
These layers are larger-scale, and copper also absorbs X-rays much more strongly than silicon.
Ah, I see. Thank you for the correction.